RTL-guided functional ECO
Implement revised RTL directly in the gate-level design without waiting for a full re-synthesis cycle.
See the RTL-to-netlist flowFunctional netlist ECO
Close the RTL change with a precise netlist patch.
GOF ECO turns a revised RTL or reference netlist into a controlled implementation-netlist patch. Generate the fix automatically, refine it in a schematic or script, and verify equivalence in the same flow.
GOF ECO / RUNCONTROLLED FLOW
Implementation netlist
Revised RTL / reference
- 01AnalyzeLocate the non-equivalent logic
- 02GenerateCreate and select the ECO patch
- 03VerifyRun equivalence checks and report
ECO netlistECO scripts
01 RTL-guided
02 Netlist-to-netlist
03 Post-layout
04 DFT-aware
Choose the constraint that matters
One ECO engine across the design cycle.
Choose RTL-guided ECO for speed or reference-netlist-driven ECO for broader changes, then carry the verified patch through post-layout and DFT netlists.
02 / NETLISTMost widely used
Netlist-to-netlist automatic ECO
Compare a re-synthesized reference netlist with the implementation netlist. This established flow is slower than RTL-guided ECO, but handles larger and more extensive logic changes.
End-to-end path ~2 days when full reference re-synthesis is required
See the reference-netlist flowPost-layout metal-only ECO
Map a verified patch onto available standard or gate-array spare cells while respecting a fixed placement.
See the post-layout flowDFT-aware ECO
Constrain test modes, preserve scan connectivity, and explicitly stitch new flops into scan chains when required.
See the DFT-aware flowFrom change to handoff
A reviewable ECO flow.
Each stage produces information you can inspect: mapped differences, the selected patch, equivalence results, and implementation outputs.
- 01
Load the design context
Read the implementation, revised RTL or reference netlist, libraries, and optional LEF/DEF physical data.
- 02
Find the functional difference
Map hierarchy and endpoints, then isolate the logic that must change, including synthesis-optimized and boundary-optimized logic.
- 03
Build the patch
Evaluate structure, reorder, and cut-point strategies; select a compact patch and refine it with GUI or Perl APIs when needed.
- 04
Verify and export
Check equivalence, review the ECO report, and write the updated netlist plus scripts for downstream implementation.
Control when the case demands it
Automate the routine. Inspect the difficult logic.
Automatic ECO provides a complete design view and generates candidate patches. For focused or repeated changes, the same design database is available through an incremental schematic and Perl-compatible scripting APIs.
Explore GUI and Script ModeAutomatic mode
Analyze non-equivalence and choose a patch strategy across the design.
GUI mode
Trace the affected cone and edit directly on the incremental schematic.
Script mode
Automate repeated changes and design queries with netlist-processing APIs.
Mixed mode
Combine targeted preprocessing with automatic patch generation in one run.
Measured production-scale case
One RTL condition. 2.3M instances. One added gate.
A post-layout SoC state-machine ECO completed with GOF 11.8. The first automatic run generated a reusable patch; the same script was then applied to the post-layout and DFT netlists.
2.3Mdesign instances
30 minfirst automatic ECO
1 AOI21gate added
PASSSynopsys Formality
THE CHANGE
Modify one transition in the xs_control state machine.
The 15-clock-domain design initially reported four non-equivalent points in the cur_state flops. The ECO adds hci_en to the transition condition in state NOV2.
NOV2:
- if (noverlap_clr) begin
+ if (noverlap_clr & hci_en) begin
if (vci_en)
nxt_state = FSM_VCI;
else
nxt_state = FSM_VGH;
end
GOF 11.8
Compute 32 CPU cores
Peak memory 15 GB
Mode RTL-guided automatic
THE RESULT
Generate once, then replay on implementation netlists.
- 01
Compare RTL and generate the patch on the 412 MB pre-layout netlist.
- 02
Export the ECO script for review and deterministic replay.
- 03
Apply the script to each post-layout or DFT netlist in 5–10 minutes.
- 04
Verify equivalence against the synthesized revised RTL with Synopsys Formality.
ECO Report for 'apu_sm_eco'
MODULE xs_control
Added wires 1
Added instances 1 AOI21
Modified instances 1
Deleted instances 0
Failing points 0View the core GOF script used in this case
Generate the patch
read_library("tsmc_5nm_svt.lib");
read_rtl("-ref", "modified_apu_top.sv");
read_rtl("-imp", "original_apu_top.sv");
set_top("apu_top");
rtl_compare();
read_design("-imp", "apu_top.prelayout.gv");
set_top("apu_top");
fix_design();
report_eco();
write_perl("eco_apu_top.pl");Replay on the post-layout netlist
read_design("-imp", "apu_top.postlayout.gv");
set_top("apu_top");
run("eco_apu_top.pl");
write_verilog("eco_apu_top.post.gv");
# The same patch can be replayed on
# the DFT-inserted implementation netlist.Measured on a 2.3M-instance SoC using 32 CPU cores. The 30-minute result is the first automatic ECO run; 5–10 minutes is the subsequent script-application time per target netlist.
Patch quality starts with mapping
Fix the changed logic without pulling unrelated gates into the patch.
Physical synthesis can clone ports, invert boundary phases, or merge flops. GOF accounts for those transformations when mapping the implementation and reference designs. In the illustrated DCT/DCG case, the correct mapping keeps a one-gate change localized.
Review the detailed comparisonTechnical resources
Move from overview to implementation.
Use the manual for flow setup, the API reference for automation, and worked cases for concrete examples.
Evaluate GOF on the work that matters
Bring the ECO that is holding up your schedule.
We will review the design stage, constraints, and current blocker, then define a focused technical evaluation.