GOF ECO
Generate functional netlist patches from revised RTL or a reference netlist, including post-layout and DFT-aware flows.
Explore GOF ECOAbout NanDigits Design Automation
Purpose-built tools for changes that cannot wait.
We help chip design teams make precise changes to gate-level designs, understand the logic behind them, and verify the result. Our GOF platform brings netlist ECO, equivalence checking, schematic debug, and fault verification into one workflow.
What we build
A connected platform for netlist engineering.
GOF gives engineers a way to move from a requested design change to a patch they can inspect and verify.
GOF LEC
Check logic equivalence and investigate non-equivalent points as part of the ECO workflow.
Explore GOF LECGOF Debug
Trace signals through large netlists, inspect dynamic schematics, and make focused GUI changes.
Explore GOF DebugGOF Formal
Use formal fault verification to evaluate functional safety coverage.
Explore GOF FormalOur approach
Built around the engineer's real workflow.
Since our first product launch in 2008, we have focused on the difficult work that follows a late design change: finding the right logic, making a small, controlled patch, and checking that the implementation still behaves as intended.
Today, we are extending that workflow with GOF AI, which lets engineers use an agentic CLI to prepare and run GOF scripts from natural-language requests. The generated scripts and verification results remain available for review.
See GOF AIOur customers
Trusted where a netlist change matters.
Design teams have used GOF for functional netlist ECO across more than 100 tapeouts. We work with engineers who need a practical path from change request to verified implementation.
Read customer perspectives
FROM THE DESIGN CHANGE TO THE VERIFIED RESULT
- Understand the design
- Make the change
- Verify the outcome
Let's talk
Have a challenging netlist ECO?
Tell us about your design and the change you need to make. We can help you evaluate the right GOF flow.