This use case shows how to calculate register driven by gated clock percentage
## Script: gated_clock_percentage.pl ## Calculate the clock gated registers percentage ## use strict; read_library("libdir/hvt.lib", "libdir/rvt.lib"); read_design("-imp", "netdir/netlist.v"); our $total_reg_num = 0; our $gated_reg_num = 0; set_quiet(1); my @tops = get_roots(); my $top = $tops[0]; &go_through_module($top); my $ratio; my $st_ratio; if($total_reg_num){ $ratio = $gated_reg_num / $total_reg_num; $ratio *= 100; $st_ratio = sprintf("%2.2f", $ratio); print "Overall, gated clock percentage $st_ratio% ($gated_reg_num / $total_reg_num)\n"; } exit; ## ## recursively go through the modules to get registers ## sub go_through_module{ my ($top) = @_; set_top($top); # get all flops in $top module my @ffs = get_cells("-type", "ff"); my $subtotal = scalar(@ffs); my $subgated = 0; $total_reg_num += $subtotal; foreach my $ff (@ffs){ my $ref = get_ref($ff); my @clks = get_pins($ref, "-clock"); my $clock_pin = $clks[0]; my @driver = get_driver("$ff/$clock_pin"); my $drive_inst = $driver[0]; if($drive_inst eq ""){ # not driven by leaf cell next; } my @types = get_cell_info($drive_inst, "-type"); if(scalar(@types)==1 && $types[0] eq "cg"){ $gated_reg_num++; $subgated++; } } if($subtotal){ my $ratio = $subgated / $subtotal; $ratio *= 100; my $st_ratio = sprintf("%2.2f", $ratio); print "Module $top has gated clock percentage $st_ratio% $subgated / $subtotal \n"; } ## ## Do each hierarchical sub module ## my @sub_instances = get_instances; foreach my $instance (@sub_instances){ set_top($top); my $sub_module = get_ref($instance); &go_through_module($sub_module); } }