Verilog to Spice naming collision

Verilog is case sensitive, while Spice is not. When converting Verilog netlist to Spice netlist, there may be naming collision. For example, in Figure 1, N100 and n100 are two different nets in the Verilog netlist. After converting to the Spice netlist, N100 and n100 are the same net in Spice syntax. And it makes the Spice netlist not equal to the original Verilog netlist.

# GOF script, convert_net_name.pl

use strict;

read_library("tsmc.lib");# Read in standard library

read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO

set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP

my @modules = get_modules("-hier");

my $cnt = 0;

foreach my $mod (@modules){

  set_top($mod);

  my @nets = get_nets("N*");

  foreach my $net (@nets){

    my $lc_net = lc($net);

    if(exist_wire($lc_net)){

      my $newname = $lc_net."_rename";

      rename_net($net, $newname);

      $cnt++;

      gprint("$cnt: In module $mod net $net renamed to $newname\n");

    }

  }

}

set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP

write_verilog("name_converted.v");