Lockup insertion in DFT ECO

Lockup latch/flop is inserted in two kinds of locations in DFT flow. One kind is between two flops that have different clock domains. The other kind is in scan output ports. This metal only ECO case is to insert lockup flops in the scan output ports of one design that has missed lockup insertion in the scan outputs.

The lockup flops are inserted by GOF ECO script. The flops are mapped to gate array spare cells in the proper positions. The ECO would be hard to be done by standard spare cells, because designers normally won't insert lots of spare cells in latch or negedge flop type. Since gate array spare cells can be configured to many types of logic functions, including negedge flop in this ECO case, this metal only ECO becomes easy to implement.

# GOF script, dft_insert_lockup.pl
use strict;
read_library("tsmc.lib");# Read in standard library
read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO
set_top("SOC_TOP"); # Set the top to the most top module SOC_TOP
my @so_ports = get_ports("scan_out*");
my $so_num = scalar(@so_ports);
foreach my $so (@so_ports){
  my @drv = get_driver($so, "-nonbuf");
  my $drv_flop = $drv[0];
  my $drv_pin = $drv[1];
  my $lockup_inst = $so;
  $lockup_inst =~ s/\W/_/g;
  $lockup_inst .= "_lockup";
  gprint("Inserting negedge flop as lockup to SO $so driven by $drv_flop/$drv_pin\n");
  change_pin("$drv_flop/$drv_pin", "GDFFNQ_X1M_A9TH50", $lockup_inst, "$drv_flop/CK,-"); 
}
read_lef("cell_lib.lef");
read_def("soc_top.def");
save_session("dft_insert_lockup");
get_spare_cells("-gate_array", "G*", "-gate_array_filler", "GFILL*");
map_spare_cells(); 
report_eco();
write_verilog("eco_verilog.v");# Write out ECO result in Verilog
exit;

The script finds 24 scan output ports and inserts 24 lockup flops. After mapping to GFILLER, total 96 tiles have been used

# ECO log file

...

FILLER_impl1_594 (GFILL4_A9TH50) @(156.18, 12.6) 4 Tiles used by the following instances. Fully used, deleted

   u_gmii_tio/scan_out_12__lockup (GDFFNQ_X1M_A9TH50) TILE X 4

FILLER_impl1_14075 (GFILL4_A9TH50) @(70.49, 185.22) 4 Tiles used by the following instances. Fully used, deleted

   u_mactop/u_prov_rst/scan_out_16__lockup (GDFFNQ_X1M_A9TH50) TILE X 4

 FILLER_impl1_47975 (GFILL4_A9TH50) @(129.39, 579.6) 4 Tiles used by the following instances. Fully used, deleted

   u_mactop/u_creg/u_rdl/scan_out_22__lockup (GDFFNQ_X1M_A9TH50) TILE X 4

FILLER_impl0_376 (GFILL8_A9TH50) @(91.96, 16.38) 4 Tiles used by the following instances. Changed to GFILL4_A9TH50

   u_gre/u_dpth/u_fifo/scan_out_13__lockup (GDFFNQ_X1M_A9TH50) TILE X 4

Added Gates Used Total Tile Numbers: 96

Checking two inserted lockup flops on the placement, they are all in the optimal positions.

Insert Lockup Cells in DFT ECO