module testtop(/*AUTOARG*/
// Outputs
foval,
// Inputs
rst, twk, in2, in1, clk, clk2, cen, ben, aen
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input			aen;			// To algo of algo.v, ...
input			ben;			// To algo of algo.v, ...
input			cen;			// To algo of algo.v, ...
input			clk, clk2;			// To algo of algo.v, ...
input [7:0]		in1;			// To algo of algo.v
input [7:0]		in2;			// To algo of algo.v
input [7:0]		twk;			// To algo of algo.v
input			rst;			// To algo of algo.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [8:0]		foval;			// From ppro of ppro.v
// End of automatics
wire [8:0] adval;
algo algo(/*AUTOINST*/
	  // Outputs
	  .adval			(adval[8:0]),
	  // Inputs
	  .clk				(clk),
	  .rst				(rst),
	  .in1				(in1[7:0]),
	  .in2				(in2[7:0]),
	  .twk				(twk[7:0]),
	  .aen				(aen),
	  .ben				(ben),
	  .cen				(cen));
ppro ppro(/*AUTOINST*/
	  // Outputs
	  .foval			(foval[8:0]),
	  // Inputs
	  .clk				(clk),
	  .clk2				(clk2),
	  .rst				(rst),
	  .adval			(adval[8:0]),
	  .aen				(aen),
	  .ben				(ben),
	  .cen				(cen));
endmodule // testtop

module algo(/*AUTOARG*/
// Outputs
adval,
// Inputs
clk, rst, in1, in2, twk, aen, ben, cen
);
input clk;
input rst;
input [3:0] in1;
input [3:0] in2;
input [7:0] twk;
input aen, ben, cen;
output [8:0] adval;
reg [8:0] adval;

wire [1:0] twk_inc;
assign twk_inc = twk[7:6] + 1'b1;

always @(posedge clk or posedge rst) begin
   if(rst) adval <= 9'h0;
   else if(twk_inc == 2'b10) adval <= in1 * in2 + aen;
   else adval <= {in1[3:0], in2[3:0]};
end

endmodule 

module ppro(/*AUTOARG*/
// Outputs
foval,
// Inputs
clk, clk2, rst, adval, aen, ben, cen
);
input clk, clk2;
input rst;
input [8:0] adval;
output [8:0] foval;
input aen, ben, cen;

reg [8:0] foval;
wire buf_ben;
BUFX10 NOTCH0(.A(ben),.Y(buf_ben));


GC100 gclk(.enable(aen),.ck_in(clk),.ck_out(iclk),.se(1'b0));
always @(posedge iclk or posedge rst) begin
   if(rst) foval <= 9'h40;
   else foval <= buf_ben? adval : ~adval;
end

endmodule 

module GC100(enable, ck_in, ck_out, se); //, test);
input enable, ck_in, se; //, test;
output ck_out;
TLATNTSCAX12 CGINST(.E(enable), .CK(ck_in), .ECK(ck_out), .SE(se));
endmodule // CG_100
